1. Field of the Invention
The present invention relates to a semiconductor device, for example, an insulated gate type field effect transistor, especially a high-power vertical MOSFET.
2. Description of the Related Art
In recent years, vertical power MOSFETs prepared using a silicon single crystal have been used widely as a power transistor. In order to reduce the occurrence of loss in the power transistor, it is necessary to reduce the ON resistance. For this purpose. a trench gate type power MOSFET shown in FIG. 7 has been proposed as a device structure capable of effectively reducing the ON resistance (for example, Japanese Unexamined Patent Publication (Kokai) No. 59-8374). In the trench gate type power MOSFET, an n type epitaxial layer 21 is provided on an n type semiconductor substrate 20, a p type diffused layer 22 is provided on the n type epitaxial layer 21 and an n type diffused layer 23 is provided in the p type diffused layer 22 in its predetermined region. Further, a trench 24 is provided which extends through the n type diffused layer 23 and the p type diffused layer 22 into the n type epitaxial layer 21. The trench 24 in its interior is filled with a polysilicon layer 26 through a gate oxide layer 25. An oxide layer 27 is provided on the upper surface of the polysilicon layer 26, and an aluminum layer 28 is formed on the n type diffused layer 23 including the surface of the oxide layer 27.
In this case, with respect to the trench gate portion, after the formation of a trench 24, the surface of the trench 24 is thermally oxidized to form a gate oxide layer 25 in the trench on its side faces and bottom face, and, thereafter, a gate electrode (a polysilicon layer 26) is formed to complete the fundamental structure of the trench gate. In the above step of oxidizing the surface of the trench 24, the thickness of the oxide layer in the portion located on the side face of the trench 24 should be thin (for example, 50 nm) in order to set the gate threshold voltage at a low value. In the case of silicon wherein the dependency of the oxidation rate upon the direction of the plane is small, the oxide layer, located on the bottom face of the trench 24, formed simultaneously with the formation of the oxide layer located on the side face of the trench 24 is as thin as the oxide layer located on the side face of the trench 24. For this reason, the thin oxide layer located on the bottom face of the trench 24 sandwiched between a low-potential gate electrode and a high-potential drain layer is likely to cause breakdown, making it difficult to prepare a trench gate type power MOSFET having a high resistance to voltage.
A known method for solving this problem is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 2-102579. This method involves repeating, a plurality of times, the step of forming an oxide layer and the step of forming an oxidation-resistant mask on the side face of the trench so that the thickness of the oxide layer is small in the portion located on the side face of the trench with the thickness thereof in its portion located on the bottom face being large, thereby preparing a trench gate type power MOSFET having a combination of low gate threshold voltage with high resistance to voltage. The steps of this method will now be described in detail with reference to FIGS. 8 to 16.
At the outset, as shown in FIG. 8, an n type epitaxial layer 31 is formed on a low-resistance n.sup.+ type semiconductor substrate 30, and a p type diffused layer 32 is formed on the n type epitaxial layer 31. Thereafter, a first oxide layer 33 is formed by thermal oxidation on the p type diffused layer 32. Then, as shown in FIG. 9, the first oxide layer 33 is patterned by photolithography to remove the first oxide layer to a given width. Thereafter, a trench 34 extending through the p type diffused layer 32 into the n type epitaxial layer 31 is formed by reactive ion etching (RIE) using the first oxide layer 33 as a mask.
Subsequently, as shown in FIG. 10, the first oxide layer 33 is removed, and a second oxide layer 35 is formed by thermal oxidation on the upper surface of the p type diffused layer 32 and the surface of the trench 34. Further, a silicon nitride layer 36 and a third oxide layer 37 are successively formed on the second oxide layer 35.
Thereafter, as shown in FIG. 11, the third oxide layer 37, the silicon nitride layer 36, and the second oxide layer 35 are successively subjected to anisotropic etching by RIE to leave as a side wall the second oxide layer 35, the silicon nitride laver 36, and the third oxide layer 37 on the side wall of the trench 34 with the other portions thereof being entirely removed.
Then, as shown in FIG. 12, the silicon nitride layer 36 in its portion located on a corner portion 34a at the bottom of the trench 34 is etched away with hot phosphoric acid.
Subsequently, as shown in FIG. 13, the third oxide layer 37 is removed with hydrofluoric acid, and a fourth oxide layer 38 is formed by thermal oxidation on the surface of the trench 34, except for the portion where the silicon nitride layer 36 is disposed, and on the p type diffused layer 32.
Thereafter, as shown in FIG. 14, the silicon nitride layer 36 is removed with hot phosphoric acid, and a gate oxide layer 39 is then formed in that portion by thermal oxidation.
Subsequently, as shown in FIG. 15, the interior of the trench 34 is successively filled with a first polysilicon layer 40 and a second polysilicon layer 41.
Thereafter, as shown in FIG. 16, the fourth oxide layer 38 located on the p type diffused layer 32 is etched away, and a low-resistance n.sup.+ type diffused layer 42 is formed in the p type diffused layer 32. Thereafter, a fifth oxide layer 43 is formed by thermal oxidation on the first and second polysilicon layers 40, 41, and an aluminum layer 44 is formed on the fifth oxide layer 43 and the n.sup.+ type diffused layer 42, thereby completing a vertical MOSFET.
Thus, a vertical MOSFET is provided which comprises an n.sup.+ type semiconductor substrate 30, a trench 34 extending through a p type diffused layer 32 and an n.sup.+ type diffused layer 42 successively laminated on the semiconductor substrate, a thin gate oxide layer 39 provided on the side face of the p type diffused layer 32 in the trench 34, a thick fourth oxide layer 38 on the other portions including a corner portion 34a in the trench 34, polysilicon layers 40, 41 buried in the trench 34, and an aluminum layer 44 deposition-formed as the outermost layer.
The above conventional method enables the insulation layer on the side face of trench 34, except for the corner portion of the trench 34 at its bottom, to be formed thin with the insulation layer on the bottom of the trench 34 including the corner portion of the trench 34 being formed thick. By virtue of this, the threshold voltage can be lowered, and, at the same time, high resistance to voltage can be attained, preventing deterioration in the semiconductor device derived from poor resistance to voltage.
In the preparation of a trench gate type power MOSFET having low threshold voltage and high resistance to voltage by the above conventional method using silicon as a semiconductor material, however, a complicated production process involving the step of repeating in a plurality of times oxidation and formation of an oxidation-resistant layer should be provided in order to form, within the trench 34, an insulation layer having a small thickness in its portion formed on the side face of the trench 34 with the thickness of the insulation layer in its portion formed on the bottom of the trench 34 being large. This raises problems of high production cost and low production yield.